This application relies for priority upon Korean Patent Application No. 2001-47667, filed on Aug. 8, 2001, the contents of which are hereby incorporated by reference in their entirety.
The present invention relates to a ferroelectric memory device having a ferroelectric capacitor such as in a ferroelectric random access memory (FRAM) and a method of forming the same.
When an external electric field is applied to a ferroelectric substance, a polarization is generated in the ferroelectric substance. Although the external electric field is removed, a significant amount of the polarization remains therein. Additionally, direction of self polarization therein can be controlled by changing the external electric field. A ferroelectric substance can be obtained by processing a high dielectric material such as PZT[Pb(Zi,Ti)O3] and SBT[SrBiTa2O9]. The physical characteristics of the ferroelectric substance are similar to the basic principle of a binary memory device. Thus, a memory device using a ferroelectric substance, such as a ferroelectric random access memory(FRAM), has been frequently investigated.
In order to form a ferroelectric substance, the high dielectric material such as the PZT or the SBT should have a ferroelectric crystalline structure called a xe2x80x9cperovskite structurexe2x80x9d. In a conventional method of forming the perovskite structure, the ferroelectric substance is stacked in an amorphous state, heated up to a high temperature (for example, about 700xc2x0 C.) in an oxidation ambient, and crystallized. However, even after the perovskite structure is formed, if physical impact occurs such as by anisotropical etching in a subsequent process, or if a certain material such as hydrogen penetrates into the ferroelectric layer by diffusion, this may cause serious damage to the characteristics of the ferroelectric substance.
More particularly, if a patterning, etching process for forming a capacitor is performed with respect to a ferroelectric layer having a ferroelectric structure, a ferroelectric layer at a peripheral part of the capacitor is damaged. This decreases capacitance of the capacitor, particularly where the capacitor size of a memory device using the ferroelectric layer is small according to the high integration of a semiconductor device.
In order to solve this problem, a method that eliminates patterning of a ferroelectric layer has been recently considered. In this method, a lower electrode is patterned and a capacitor dielectric layer is stacked thereon. Then, without patterning the dielectric layer, an upper electrode layer is stacked and patterned to form an upper electrode.
In another method of preventing degradation of a ferroelectric layer, a curing thermal process can be performed on a ferroelectric layer that is damaged by the patterning process. Specifically, at a suitable temperature, which is lower than a temperature for forming the perovskite structure of a ferroelectric layer, a thermal process is performed in an oxygen ambient to cure the damage resulting from patterning the ferroelectric layer. FIG. 1 illustrates a graph indicating ferroelectric recovery according to a thermal process temperature and applied voltage in a thermal process performed after patterning a ferroelectric layer. As shown in FIG. 1, when the temperature of the thermal process is the same, if an applied voltage is high, the polarization region is high. And, when the applied voltage is the same, if a temperature of the thermal process is high, the polarization region is much higher. That is, according to this graph, as the applied voltage increases, and as the temperature of the thermal process increases, an average value of the polarization increases.
However, although the ferroelectric layer is not etched and patterned, the ferroelectric structure can be damaged during a subsequent patterning process for forming an upper electrode. Additionally, the curing thermal process can degrade conductivity between a capacitor electrode and a contact. That is, since the curing thermal process is performed in an oxygen ambient of high temperature, a conductive material is oxidized at an electrode or a contact interface related to a storage node capacitor, thereby creating an insulation material and increasing resistance. This prevents normal operation.
FIG. 2 illustrates a partial cross-sectional view showing a structure of a cell capacitor of a FRAM device to explain an example of the above-described problem. Referring to FIG. 2, a conductive plug 20 is formed through an interlayer dielectric layer 10 formed on a semiconductor substrate (not shown), and a capacitor is formed on and covering the conductive plug 20. The capacitor is composed of an adhesive assistant pattern 30 formed of a thin titanium layer covering the conductive plug 20 and the interlayer dielectric layer 10 peripheral to the conductive plug 20, a lower electrode 40, a ferroelectric pattern 50, and an upper electrode 60. The lower and upper electrodes 40 and 60 are formed of a single layer or a multiple layer including at least one of the noble metals, which are difficult to oxidize, or metal oxides with conductivity. Thus, each of the electrode layers is not seriously influenced by the curing thermal process, which is performed in the oxygen ambient of high temperature. However, the titanium layer of the adhesive assistant pattern 30 is exposed to the oxygen ambient of high temperature during the curing thermal process, and is changed into an insulation oxide layer. This prevents normal operation of a memory device.
In the ferroelectric memory device according to the present invention, an oxygen barrier layer is formed over cell capacitor patterns, and patterned to at least cover sidewalls of an adhesive assistant pattern in the cell capacitor patterns. The patterning of the oxide barrier layer is such that the resulting oxide barrier pattern does expose sidewalls of a ferroelectric pattern of the cell capacitor patterns. When a subsequent thermal curing operation is conducted to cure the damaged portions of the ferroelectric pattern, the oxygen barrier pattern prevents the adhesive assistant pattern from oxidizing. As a result, the contact interface resistance at the adhesive assistant pattern does not degrade, and operation error is prevented.